Field of the Invention
The invention pertains to methods for low thermal budget cure of freshly deposited polymeric films during semiconductor packaging. The method more particularly relates to the use of microwave energy for selective curing of primarily the freshly dispensed polymeric film among multiple polymeric materials used in prior semiconductor packaging steps.
Description of Related Art
Assembly and Packaging provide the means for cost effective incorporation of functional diversification through various technologies that enable continued increase in functional density and decrease in cost per function required to maintain the progress in cost and performance for electronics. New architectures that include printed circuits, thinned wafers and both active and passive embedded devices are emerging as solutions to market requirements. The materials and equipment used in assembly and packaging are also changing rapidly to meet the requirements of these new architectures and the changing environmental regulatory requirements.
Wafer level packaging (WLP) is defined as a technology in which all of the IC packaging steps are performed at the wafer level, with all package I/O terminals continuously located within the chip outline (Fan-in design) producing a true chip size package. WLP provides a solution for the situation where requirements for size, operating frequency and cost reduction cannot be met by traditional packaging (e.g. wire bonding or flip-chip bonding). There are, however, products that do not fall under the above definition of WLP. These new packages are described as “Fan-out” WLP or “embedded” WLP, and are fabricated by placing individual die into a polymer matrix that has the same form factor as the original silicon wafer. The “Reconstituted” artificial wafers are then processed through all of the same steps that are used for actual silicon wafers, and finally diced into separate packages. The die is placed in the polymer matrix such that there is a rim of polymer surrounding each die. With this technology, it is no longer only intact silicon wafers that can be processed as a “WLP”, but hybrid silicon/polymer matrices in wafer form that also can now be classified as WLP products. With die placement in a polymer matrix there becomes a need to cure the polymer material as well as a need for higher-level re-distribution layers to “fan-out” the I/O to the outside perimeter of each die.
WLP technology also includes wafer level chip size packages (WLCSP), fan-out wafer level packages, wafer capping on MEMS, wafer level packages with Through Silicon Vias (TSVs), wafer level packages with Integrated Passive Devices (IPD), and wafer level substrates featuring fine traces and embedded integrated passives. All these technologies become the building blocks for 3D Wafer Level Packages (3DWLP).
In recent years Wafer Level Packaging of CMOS image sensors has attracted substantial effort and attention. The fabrication techniques for Wafer Level Cameras (WLC) used in modern camera systems and mobile phones involve the use of Opto Wafers and CMOS-Wafers, which are mounted by Wafer Level Packaging (WLP) approaches. A typical Wafer Level Camera consists of several optical elements that need to be assembled quite accurately to provide the best possible optical performance. The packaging and replication of micro-lens wafers (opto wafers) uses UV curable materials which are currently used for mass production in the electronics and optics assembly industries. Depending on the chemical basis—acrylic or epoxy—these materials differ in some of the basic parameters. Acrylic adhesives are known to be very fast curing, but are limited at high temperature processes and have high polymerization shrinkage. On the other hand, epoxy based systems are known for good thermal stability and low shrinkage and are therefore used in high reliability applications. The challenge as seen by the industry for Wafer Level Optics (WLO) manufacturing is to develop materials or processes with fast curing mechanisms, high optical transmission and high thermal stability.
At the substrates level, fine design rules and the capability of creating integrated passive devices are attractive features. Dielectrics and traces are built on silicon substrates by wafer process technology and the following assembly is performed on the wafer level substrate. Some wafer level substrates are not made of silicon but dielectric layers and traces built up on a wafer. The Inter Layer Dielectric (ILD) materials used to electrically separate closely spaced interconnect lines are arranged in several levels (multi-level metallization) in an advanced integrated circuit. These materials must feature low dielectric constant k to minimize capacitive coupling between adjacent metal lines.
Thus, polymers are a key building block for all WLP and related technologies. Many different classes of useful polymeric materials are known, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicones, acrylates and epoxies. Curing and the resulting shrinkage also play an important role due to temperature sensitive devices and the topography of the metallization which has to be passivated.
Work is underway on materials which include but are not limited to: use of polyimide material as a temporary adhesive for bonding thinned wafers to a carrier wafer for processing; use of polyimide material as a permanent adhesive for bonding of wafer/chip stacks; use of a PBO dielectric to bond backside circuitry onto thinned wafers (for lower temperature cure avoiding damage to structures on the wafer); and new over molding compounds for semiconductor packaging materials to prevent die shift in fan-out packaging.
The use of polymeric materials in all of the areas addressed above and their lower thermal budget cure is therefore very important in wafer level packaging. There are several methods for forming thin films on substrates. The simplest and the least expensive is spin coating (e.g. of polyimide on silicon wafer), where the material (usually in solvent) is dropped on the substrate surface and spun up to 5000 rpm (usually 1500-3000), to form a uniform film (˜2-10 μm) on planar substrates only. The turntable may be allowed to rotate even after spreading the material to evaporate the solvent. Then a low temperature or “soft-bake” step (˜100° C.) is carried out to dry the film and finally followed by a higher temperature cure (e.g. >300° C. for polyimide).
Most films deposited need a heat treatment. The organic materials need to be cured well to provide optimum dielectric properties. Some heat treatments could be carried out during the deposition process or in the same chamber, but usually the cures are time consuming and hence the thermal treatment is performed separately in a following step. Thus, the thermal treatment for polymeric cure is conducted in ovens, on hot plates, or by microwave heating.
It should be pointed out that either inadequate or excessive cure of dielectric films can cause serious problems in microelectronic packaging whether curing is done by microwave, induction, conduction, or convection. If a film is incompletely cured then subsequent exposure to solvents and development chemicals will cause the leaching of uncured molecules out of the film. This causes cracking that often allows both open and shorted circuits at the microscopic level. If a film is excessively heated beyond the desired complete cure, there is decomposition and degradation of the film which also causes microscopic opens and shorts as well as modification of the dielectric and thermomechanical properties of the polymers. When either of these conditions happens in lower layers of a multilayer film, these defects are not easily seen due to the opacity of each polymer layer in its cured state. Identification of the source circuit failures in these cases is very difficult, time-consuming and expensive. If the failures happen in the field, the reliability of the product is affected.
In contrast to microwave heating, conventional heating methods are not self-limiting. In addition, conventional heating is an “outside-in” phenomenon. Heat must penetrate slowly through outside layers to reach inner layers, so the curing process of polymers completes the curing of internal molecules only after all other molecules have transferred the heat to the inside by conduction. This process produces the well-known “skinning” of over-cured outside layers that produces degradation, non-uniformity and warpage in the polymer layers.
This situation makes it difficult for practitioners to use an approach that intentionally under-cures a lower layer with the intention of that layer becoming completely cured during subsequent thermal processing. Since the cure time is much longer for each of the multiple films deposited for fabrication of a device, there is a tendency not to fully cure a prior film and let it cure completely during a subsequent heating cycle to cure the latter film. During these conventional heating steps it is common practice to use long ramp times of increasing temperature to minimize stress and warpage as much as possible. Reduced yields, high warpage, and reliability issues are common traits of polymer film curing of electronic assemblies.